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模数转换器 ADS58C48 datasheet
资料介绍
ADS58C48主要特性，方框图，模拟输入电路和多种驱动电路，以及ADS58C48EVM评估板主要特性，电路图和材料清单（BOM）。ADS58C48是TI公司的四路取样频率高达200MSPS 的11位（ADC），单电源1.8V工作，总功耗为0.9W。ADS58C48采用第三代SNRBoost3G技术，140MHz时的SFDR为82dBc，支持带宽高达60MHz，标准摆幅为350mV，主要用在各种通信设备包括遥控无线电，软件定义无线电（SDR），无线中继器以及MIMO和各种接收器。
部分文件列表
| 文件名 | 大小 |
| ads58c48.pdf | 3M |
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（完整内容请下载后查看）www.ti.com
SLAS689 –MAY 2010
Quad Channel IF 3G
Check for Samples:
1
FEATURES
DESCRIPTION
•
Maximum Sample Rate: 200 MSPS
The ADS58C48 is a quad channel 11-bit A/D
converter with sampling rate up to 200 MSPS. It uses
innovative design techniques to achieve high dynamic
performance, while consuming extremely low power
at 1.8V supply. This makes it well-suited for
multi-carrier, wide band-width communications
applications.
•
High Dynamic Performance
–
–
SFDR 82 dBc at 140 MHz
72.3 dBFS SNR in 60 MHz BW Using
SNRBoost 3G technology
•
•
SNRBoost 3G Highlights
3G
–
–
Supports Wide Bandwidth up to 60 MHz
The ADS58C48 uses third-generation SNRBoost
technology to overcome SNR limitation due to
Programmable Bandwidths – 60 MHz, 40
MHz, 30 MHz, 20 MHz
quantization noise (for bandwidths < Nyquist, Fs/2).
3G
Enhancements in the SNRBoost
technology allow
–
–
Flat Noise Floor within the Band
Independent SNRBoost 3G Coefficients for
support for SNR improvements over wide bandwidths
3G
(up to 60 MHz). In addition, separate SNRBoost
Every Channel
coefficients can be programmed for each channel.
Output Interface
The device has digital gain function that can be used
to improve SFDR performance at lower full-scale
input ranges. It includes a dc offset correction loop
that can be used to cancel the ADC offset.
–
Double Data Rate (DDR) LVDS with
Programmable Swing and Strength
–
–
–
–
Standard Swing: 350 mV
The digital outputs of all channels are output as DDR
LVDS (Double Data Rate) together with an LVDS
clock output. The low data rate of this interface (400
Mbps at 200 MSPS sample rate) makes it possible to
use low-cost FPGA-based receivers. The strength of
the LVDS output buffers can be increased to support
50-Ω differential termination. This allows the output
clock signal to be connected to two separate receiver
chips with an effective 50-Ω termination (such as the
two clock ports of the GC5330).
Low Swing: 200 mV
Default Strength: 100-Ω Termination
2x Strength: 50-Ω Termination
–
1.8V Parallel CMOS Interface Also
Supported
•
•
Ultra-Low Power with Single 1.8-V Supply
–
–
0.9-W Total Power
1.32-W Total Power (200 MSPS) with
SNRBoost 3G on all 4 Channels
The same digital output pins can also be configured
as a parallel 1.8-V CMOS interface.
–
1.12-W Total Power (200 MSPS) with
SNRBoost 3G on 2 Channels
It includes internal references while the traditional
reference pins and associated decoupling capacitors
have been eliminated. The device is specified over
the industrial temperature range (–40°C to 85°C).
Programmable Gain up to 6dB for SNR/SFDR
Trade-Off
•
•
•
DC Offset Correction
Supports Low Input Clock Amplitude
80-TQFP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
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