您现在的位置是:首页 > 技术资料 > 24LC256 EEProm datasheet
推荐星级:
  • 1
  • 2
  • 3
  • 4
  • 5

24LC256 EEProm datasheet

更新时间:2019-09-18 15:50:45 大小:618K 上传用户:eric8290查看TA发布的资源 标签:24lc256eeprom 下载积分:0分 评价赚积分 (如何评价?) 收藏 评论(0) 举报

资料介绍

介绍了24LC256EEPROM芯片的特点及主要功能,描述了其引脚定义、工作原理以及读写操做時序

部分文件列表

文件名 大小
24LC256.pdf 618K

部分页面预览

(完整内容请下载后查看)
24AA256/24LC256/24FC256  
256K I2CCMOS Serial EEPROM  
Temperature Ranges:  
- Industrial (I):  
- Automotive (E):  
Device Selection Table  
-40°C to +85°C  
-40°C to +125°C  
Part  
VCC  
Max. Clock  
Frequency  
Temp.  
Ranges  
Number  
Range  
24AA256  
24LC256  
24FC256  
1.7-5.5V  
2.5-5.5V  
1.7-5.5V  
400 kHz(1)  
400 kHz  
1 MHz(2)  
I
I, E  
I
Description:  
The Microchip Technology Inc. 24AA256/24LC256/  
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial  
Electrically Erasable PROM, capable of operation  
across a broad voltage range (1.7V to 5.5V). It has  
been developed for advanced, low-power applications  
such as personal communications or data acquisition.  
This device also has a page write capability of up to 64  
bytes of data. This device is capable of both random  
and sequential reads up to the 256K boundary.  
Functional address lines allow up to eight devices on  
the same bus, for up to 2 Mbit address space. This  
device is available in the standard 8-pin plastic DIP,  
SOIC, TSSOP, MSOP and DFN packages.  
Note 1: 100 kHz for VCC < 2.5V.  
2: 400 kHz for VCC < 2.5V.  
Features:  
• Single Supply with Operation Down to 1.7V for  
24AA256 and 24FC256 Devices, 2.5V for  
24LC256 Devices  
• Low-Power CMOS Technology:  
- Active current 400 uA, typical  
- Standby current 100 nA, typical  
• 2-Wire Serial Interface, I2CCompatible  
• Cascadable up to Eight Devices  
• Schmitt Trigger Inputs for Noise Suppression  
• Output Slope Control to Eliminate Ground Bounce  
• 100 kHz and 400 kHz Clock Compatibility  
• Page Write Time 5 ms max.  
Block Diagram  
A0 A1A2WP  
HV Generator  
I/O  
Control  
Logic  
Memory  
Control  
Logic  
EEPROM  
Array  
XDEC  
• Self-Timed Erase/Write Cycle  
• 64-Byte Page Write Buffer  
Page Latches  
• Hardware Write-Protect  
I/O  
• ESD Protection >4000V  
SCL  
YDEC  
• More than 1 Million Erase/Write Cycles  
• Data Retention >200 years  
SDA  
• Factory Programming Available  
VCC  
VSS  
• Packages Include 8-lead PDIP, SOIC, DFN,  
TSSOP and MSOP  
Sense Amp.  
R/W Control  
• Pb-Free and RoHS Compliant  
Package Types  
PDIP/SOIC  
TSSOP/MSOP*  
DFN  
A0  
1
8
VCC  
1
2
3
4
A0  
A1  
8
7
6
5
VCC  
WP  
1
2
8
7
A0  
A1  
VCC  
A1  
A2  
2
3
4
7
6
5
WP  
WP  
A2  
SCL  
SDA  
SCL  
SDA  
3
4
6
5
A2  
SCL  
SDA  
VSS  
VSS  
VSS  
Note: * Pins A0 and A1 are no connects for the MSOP package only.  
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.  
© 2007 Microchip Technology Inc.  
DS21203P-page 1  

全部评论(0)

暂无评论